1. Field of the Invention
This invention relates generally to MOS memory arrays and, more particularly, to static MOS memory arrays that utilize memory cells having four MOS devices per memory cell.
2. Description of the Prior Art
MOS memory arrays fall into two broad general categories, either dynamic or static. Dynamic MOS memory arrays require that the gates of the MOS or FET devices that make up the memory cells be periodically refreshed in order to prevent the data stored in the memory cells from being lost due to current leakage. Dynamic MOS memory cells have become very popular for use in large main frame memory systems that are connected up to a central processing unit to provide a computer system. The cost of dynamic memory cells has reduced very dramatically in recent years corresponding to the reduction in the number of MOS devices that were used to make up a memory cell. The number of MOS devices used to make up a dynamic memory cell have dropped from older memory cell designs that utilized four MOS devices to more recent memory cell designs that utilized three MOS devices to current memory cell designs that utilize only a single MOS device and a connected semiconductor capacitor device. As a result of this significant reduction in memory cell size with its correspondingly higher yields and lower costs, semiconductor MOS dynamic memory chips are today being manufactured as 4K bit chips and 16K bit chips with memory designers already planning 64K bit chips.
Static MOS memory cells are also very important to the semiconductor memory business and are used in memory arrays for systems that are not designed to permit refresh operations to be performed because of interference with the system's architecture. Furthermore, static MOS memory cells are less volatile than dynamic memory cells.
Static MOS memory cell designs have generally not undergone as rapid a change as dynamic memory cell designs. One of the early static MOS memory cell designs utilized six MOS devices connected up in a fairly elaborate circuit configuration which utilized a cross-coupled, flip-flop type of design. A later example of one of these types of six device, static, MOS memory cells is disclosed, for example, in U.S. Pat. No. 3,539,839. This patent shows a static memory cell design that utilizes four MOS devices and two resistors (instead of two MOS devices) in its six device static memory cell. The purpose and function of the two resistors (or two MOS devices) is to act as load devices and to hold the charges or stored memory state in the cross-coupled MOS or FET devices. The function of the other two MOS devices 32 and 33 of this prior art patent is for reading and writing operations.
A later static MOS memory cell design was developed which reduced the size of the six device static MOS memory cell to a four MOS device memory cell. An example of this type of four MOS device static memory cell is shown, for example, in U.S. Pat. No. 3,530,443. However, this type of memory cell required the use of three different potential sources (0, -8, and -16 volts) in order to operate the memory cell thus requiring two separate power supplies (-8 and -16 volts).
Accordingly, a need existed to provide a four device static MOS memory cell design and static MOS memory array configuration that would use only a single (5 volt) power supply to operate the memory cells of the memory array in both the standby and active conditions.